In order to preserve power resources and lower overhead usage, physical processors may utilize memory monitoring instructions designating a range of memory that allow the physical processor to stop instruction execution. The physical processor executing the monitoring instruction may be blocked from further execution and enter a wait state until there is a change to the designated memory by another physical processor or an inter-processor interrupt is received. Using the ×86 instruction set architecture as an example, this feature may include a MONITOR instruction and an MWAIT instruction. The MONITOR instruction causes the processor hardware to monitor a range of memory addresses designated by the MONITOR instruction. If there is a change to the designated memory (e.g., data storing), a signal is triggered within the processor hardware. This signal may be used by the MWAIT instruction. The MWAIT instruction causes the processor to enter a halt state until data has been written to a memory address within the range designated by the MONITOR instruction. If a processor is in a halt state as a result of the MWAIT instruction, a change to the designated memory may trigger a signal to bring that processor out of the halt state.